The electronics industry is under constant pressure to both reduce component size as well as power requirements and has a market driven need to improve operation of memory devices. One approach to reduce component size is to fabricate devices in a three-dimensional (3D) configuration. 3D memory technology, using pillar access devices and other methods, is evolving in the memory industry. Use of 3D technology enables higher density for the memory array core of a memory device with memory cells arranged vertically. For example, a memory device, such as a dynamic random access memory (DRAM), can be arranged as a stack of memory cells vertically on a substrate. As the memory array core of a DRAM is being arranged as a vertical stack for die size scaling and cost saving, the number of sense amplifiers (sense amps) is not increasing. This lack of sense amps for the vertical arrangement will hurt the refresh performance of the memory cells of the memory array. With a standard sense amp servicing multi-vertical array cores, the access to the vertical array cores becomes limited. In essence, the sense amps of the DRAM are being diluted. Improvements to 3D memories can be addressed by advances in design of the memory devices.